The current double data rate (DDR) synchronous dynamic random access memory (SDRAM) (also referred to as DRAM) standard is for DDR4 memory, and provides a channel that can support dual-in-line memory module (DIMM) devices at a maximum speed rate of 1600 MHz or 3200 mega-transactions (MT)/second (s) clocking data on both rising and falling clock edges, and next generation DDR5 memories will be up to 6400 MT/s maximum speed. Generally, however, no related DIMM devices operating at the 3200 MT/s speed have been introduced yet, even though DDR4-SDRAM chips are available with a 3200 MT/s speed rate. This is primarily because DDR4 could only support a single DIMM device on the bus at the 3200 MT/s speed. This limits the memory capacity at higher speeds to one third that of slower-speed implementations, e.g., ones running at 2400 MT/s with 3 DIMMs per channel (DPC). Further, currently expensive three dimensional stacked (3DS) DDR4-SDRAM chips are used for high capacity DIMM devices.
The DDR5 bus running in speed rate higher than 4400 MT/s could limit the loading to 1DPC with half numbers of DDR5-SDRAM chips on the DIMM device than at slow speed rate. The graphic DDR5 (GDDR5) and GDDR5X memory standards are used for graphical processing unit (GPU) with dedicated point-to-point graphic memories up to 14 GT/s speed, but they are not used for server DIMM devices.